Embedded Source/Drain SiGe Stressor Devices on SOI: Integrations, Performance, and Analyses

Author

Da Zhang ; White, Ted ; Nguyen, Bich-yen

Author_Institution

Technol. Solutions Organ., Freescale Semicond., Austin, TX

Volume

53

Issue

12

fYear

2006

Firstpage

3020

Lastpage

3024

Abstract

A detailed investigation of embedded source/drain SiGe stressors (eSiGes) on a silicon-on-insulator substrate for pMOS performance enhancement is presented. It is found that the integration with undoped SiGe epitaxy suffers strain relaxation from a postepitaxy implantation. SiGe growth with in situ doping is able to retain high strain for carrier mobility enhancement. For doped eSiGe integration with a proper thermal sequence, 20% pMOS drive current improvement is demonstrated. Quantitative analyses of contributions from mobility enhancement and device exterior resistance reduction to the performance improvement are also discussed

Keywords

Ge-Si alloys; MOSFET; carrier mobility; ion implantation; semiconductor doping; silicon-on-insulator; SOI; SiGe; carrier mobility enhancement; device exterior resistance reduction; embedded source/drain SiGe stressor devices; in situ doping; pMOS performance enhancement; postepitaxy implantation; silicon-on-insulator substrate; strain relaxation; thermal sequence; undoped SiGe epitaxy; Annealing; CMOS technology; Capacitive sensors; Doping; Epitaxial growth; Germanium silicon alloys; Performance analysis; Silicon germanium; Silicon on insulator technology; Substrates; in situ doping; Embedded source/drain (S/D) stressor; SiGe epitaxy; mobility enhancement; silicon-on-insulator (SOI); strain;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.885534

Filename

4016368