A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs

A compact RF CMOS model incorporating an improved thermal noise model is developed. Short-channel effects (SCEs), substrate potential fluctuation effect, and parasitic-resistance-induced excess noises were implemented in analytical formulas to accurately simulate RF noises in sub-100-nm MOSFETs. The intrinsic noise extracted through a previously developed lossy substrate de-embedding method and calculated by the improved noise model can consistently predict gate length scaling effects. For 65- and 80-nm n-channel MOS with f_T above 160 and 100 GHz, NF_min at 10 GHz can be suppressed to 0.5 and 0.7 dB, respectively. Drain current noise S_id reveals an apparently larger value for 65-nm devices than that for 80-nm devices due to SCE. On the other hand, the shorter channel helps reduce the gate current noise S_ig attributed to smaller gate capacitances. Gate resistance R_g-induced excess noise dominates in S_ig near one order higher than the intrinsic gate noise that is free from R_g for 65-nm devices. The compact RF CMOS modeling can facilitate high-frequency noise simulation accuracy in nanoscale RF CMOS circuits for low-noise design.