• DocumentCode
    84001
  • Title

    Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

  • Author

    Liu, Tsung-Yen ; Lo, S.-C. ; Sheu, Jeng-Tzong

  • Author_Institution
    Department of Materials Science and Engineering, Institute of Nanotechnology, National Chiao Tung University, Hsinchu, Taiwan
  • Volume
    34
  • Issue
    4
  • fYear
    2013
  • fDate
    Apr-13
  • Firstpage
    523
  • Lastpage
    525
  • Abstract
    We investigate the characteristics of single-crystal-like (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon ( \\alpha -Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 \\mu{\\rm m} lead to clear improvement in electrical performance, including a steep subthreshold swing (90\\pm 15~{\\rm mV}/{\\rm dec}) , a virtual absence of drain-induced barrier lowering (21\\pm 13~{\\rm mV/V}) , and a very high ON/OFF current ratio {\\sim}{7}\\times 10^{7}~(V_{\\rm D}=1~{\\rm V},~{\\rm V}_{\\rm G}=3~{\\rm V}) .
  • Keywords
    Logic gates; Performance evaluation; Plasmas; Silicon; Thin film transistors; Gate-all-around (GAA); nanowire (NW); single-crystal-like (SCL); thin film transistor (TFT);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2013.2247737
  • Filename
    6475961