DocumentCode :
840165
Title :
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design
Author :
Fetzer, E.S.
Author_Institution :
Intel
Volume :
23
Issue :
6
fYear :
2006
fDate :
6/1/2006 12:00:00 AM
Firstpage :
476
Lastpage :
483
Abstract :
With each successive technology generation, process and environmental variations consume an increasingly large portion of the design envelope. To mitigate the impact of these variations, designs can incorporate adaptive techniques to reduce the impact. At the core of adaptability is the fundamental idea that each piece of silicon is different and will respond differently to stimuli. This poses a significant challenge in testing the product because testing relies on all parts behaving in a predictable manner every time they are tested. This article details adaptive techniques used on a dual-core, 90-nm Itanium microprocessor, and the issues and limitations encountered when testing this design.
Keywords :
Aging; Central Processing Unit; Circuit optimization; Clocks; Integrated circuit interconnections; Microprocessors; Power system interconnection; Program processors; Temperature; Voltage; Itanium microprocessor; Montecito; active clock deskew; adaptive circuits; cache safe technology; dual core; power measurement; process variation;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
F9431248-0ACC-43CA-AB0B-3CAEB5CD0E5A
Filename :
4016455
Link To Document :
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