Title :
Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs
Author :
Kuppambatti, Jayanth ; Kinget, Peter R.
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
Current pre-charging techniques are introduced to generate the reference in MDACs of pipeline ADCs. They are specifically applied to zero-crossing-based (ZCB) pipeline-SAR ADCs in this paper. The proposed reference pre-charge technique relaxes power and area requirements for reference voltage generation and distribution in ZCB Pipeline ADCs, by eliminating power-hungry low-impedance reference voltage buffers. Dynamic reference loading (DRL), a variant of current reference pre-charging, is further proposed to reduce the loading due to the reference capacitors leading to improvements in the ADC noise performance. A proof-of-principle reference pre-charged DRL ZCB Pipelined-SAR ADC, implemented in 65 nm CMOS, shows an SFDR/SNR/SNDR of 77 dB/70 dB/66 dB at 25 MHz, while consuming 4.8 mW at 50 MS/s for an FOM of 57 fJ/step. The ADC does not require any additional power and/or area for reference voltage generation and distribution.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; reference circuits; ADC noise performance; CMOS integrated circuit; ZCB pipeline ADC; analog-digital converter; current reference precharging technique; low power SAR ADC; pipeline SAR ADC; power 4.8 mW; reference voltage generation; size 65 nm; successive approximation register; zero crossing SAR ADC; Capacitors; Clocks; Loading; Pipelines; Signal to noise ratio; System-on-chip; CMOS integrated circuits; SAR; pipeline; reference pre-charging; zero-crossing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2014.2299632
