Pattern Based Prediction for Plasma Etch

Author

Abrokwah, Kwaku O. ; Chidambaram, P.R. ; Boning, Duane S.

Author_Institution

Microsystems Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA

Volume

20

Issue

2

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

77

Lastpage

86

Abstract

Plasma etching is a key process for pattern formation in integrated circuit (IC) manufacturing. Unfortunately, pattern-dependent nonuniformities arise in plasma etching processes due to localized microloading and feature size or aspect ratio-dependent reactive ion etch lag. We propose a semi-empirical methodology for characterization and chip-scale modeling of pattern-dependent effects in plasma etching of ICs. We apply this methodology to the study of interconnect trench etching and show that an integrated model is able to predict both pattern density and feature size dependent nonuniformities in trench depth

Keywords

chip scale packaging; integrated circuit interconnections; integrated circuit modelling; sputter etching; IC manufacturing; aspect ratio-dependent; chip-scale modeling; integrated circuit manufacturing; interconnect trench etching; pattern based prediction; pattern density; pattern formation; pattern-dependent effects; pattern-dependent nonuniformities; plasma etching processes; reactive ion etch lag; semiempirical methodology; Etching; Filters; Instruments; Manufacturing processes; Pattern formation; Plasma applications; Plasma density; Plasma materials processing; Predictive models; Semiconductor device modeling; Aspect ratio dependent etch (ARDE); die level variation; feature level variation; microloading; pattern density; pattern dependency; reactive ion etch (RIE);

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2007.896638

Filename

4182418