DocumentCode
84076
Title
Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclamped Inductive Switching
Author
Breglio, G. ; Irace, A. ; Napoli, E. ; Riccio, M. ; Spirito, P.
Author_Institution
Dept. of Biomed., Electron. & Telecommun. Eng., Univ. of Naples Federico II, Naples, Italy
Volume
60
Issue
2
fYear
2013
fDate
Feb. 2013
Firstpage
563
Lastpage
570
Abstract
The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the IC- VCE curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer.
Keywords
current density; electric resistance; failure analysis; insulated gate bipolar transistors; numerical analysis; semiconductor device testing; switching; 3D electrothermal numerical simulations; NDR region; NPT trench IGBT structure; PT; UIS limit; UIS test; current density; current-limited failures; device failure; different failure mechanisms; energy limitation; experimental detection; failure modes; field-stop layer; filamentary current conduction; insulated-gate bipolar transistor structures; latch-up failure; local lifetime control; low time duration; maximum avalanche capability; negative differential resistance region; not punchthrough; numerical validation; punchthrough; unclamped inductive switching; Current density; Electric breakdown; Heating; IP networks; Insulated gate bipolar transistors; Numerical models; Numerical simulation; Insulated-gate bipolar transistors (IGBTs); power semiconductor switches; semiconductor device reliability; semiconductor device testing;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2226177
Filename
6374242
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