CMOS Latch Using Quad for High-Speed Comparators

Author

Acharya, Venkatesh ; Viswanathan, T.Lakshmi ; Viswanathan, T.R.

Author_Institution

Texas Univ., Richardson, TX

Volume

54

Issue

5

fYear

2007

fDate

5/1/2007 12:00:00 AM

Firstpage

407

Lastpage

411

Abstract

The well-known CMOS quad consisting of two asymmetric differential pairs is a transconductance element. It provides an additional output current proportional to the square of its differential input voltage. Here, we use both the linear and square-law outputs of a quad to build a high-speed latch that has differential low-voltage output swing. This latch retains the useful property of constant power-supply current like all current-biased differential current-mode logic circuits. Simulation results for 0.18-mum CMOS process are presented. The design is application specific and is intended for use in high-speed comparators needed for analog-to-digital converters

Keywords

CMOS logic circuits; analogue-digital conversion; comparators (circuits); current-mode logic; flip-flops; 0.18 micron; CMOS latch; CMOS quad; analog-to-digital converters; asymmetric differential pairs; bistable circuits; bistable multivibrator; differential current-mode logic circuits; flip-flops; high speed comparators; transconductance element; CMOS process; Circuit simulation; FETs; Flip-flops; Latches; Logic circuits; Pulse circuits; Semiconductor device modeling; Transconductance; Voltage; Bistable circuits; bistable multivibrator; comparators; flip-flops; integrated circuits; latches;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2007.892209

Filename

4182492