DocumentCode
841714
Title
An improved branch and bound algorithm for exact BDD minimization
Author
Ebendt, Rüdiger ; Günther, Wolfgang ; Drechsler, Rolf
Author_Institution
Dept. of Comput. Sci., Kaiserslautern Univ., Germany
Volume
22
Issue
12
fYear
2003
Firstpage
1657
Lastpage
1663
Abstract
Ordered binary decision diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of the BDDs depends on a chosen variable ordering, i.e., the size may vary from linear to exponential, and the problem of Improving the variable ordering is known to be NP-complete. In this paper, we present a new exact branch and bound technique for determining an optimal variable order. In contrast to all previous approaches that only considered one lower bound, our method makes use of a combination of three bounds and, by this, avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from very large scale integration design. They allow one to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.
Keywords
Boolean functions; VLSI; binary decision diagrams; formal verification; logic CAD; minimisation of switching nets; tree searching; Boolean functions; NP-complete; VLSI computer-aided design; data structure; exact BDD minimization; formal verification; improved branch and bound algorithm; logic synthesis; optimal variable order; ordered binary decision diagrams; pass transistor logic; Binary decision diagrams; Boolean functions; Computer science; Costs; Data structures; Formal verification; Logic; Minimization methods; Runtime; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2003.819427
Filename
1253544
Link To Document