A pixel size shrinkage of amplified MOS imager with two-line mixing

Author

Yamawaki, Masao ; Kawashima, Hiroshi ; Murata, Naofumi ; Andoh, Fumihiko ; Sugawara, Masayuki ; Fujita, Yoshihiro

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

43

Issue

5

fYear

1996

fDate

5/1/1996 12:00:00 AM

Firstpage

713

Lastpage

719

Abstract

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-μm CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 μA/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)×5.6 (V) μm². Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively

Keywords

CMOS integrated circuits; image sensors; integrated circuit layout; integrated circuit technology; ion implantation; photodiodes; sensitivity; 0.25 in; 0.8 micron; 2.5E5 pixel; 4 V; 6 V; CMOS process; amplified MOS imager; high sensitivity; image sensor; ion-implantation process; pixel size shrinkage; resetting MOSFET; two-line mixing; Ambient intelligence; CMOS process; Circuits; Dynamic range; Image sensors; Length measurement; Noise measurement; Pixel; Power supplies; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.491247

Filename

491247