• DocumentCode
    842249
  • Title

    Improving Linear Test Data Compression

  • Author

    Balakrishnan, Kedarnath J. ; Touba, Nur A.

  • Author_Institution
    NEC Labs. America, Princeton, NJ
  • Volume
    14
  • Issue
    11
  • fYear
    2006
  • Firstpage
    1227
  • Lastpage
    1237
  • Abstract
    The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells while reconfiguration modifies the linear decompressor. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed methods improve the compression further. The key property of scan inversion is that it is a linear transformation of the output space and, thus, the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize compression. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for reconfiguring the linear decompressor. The proposed schemes can be utilized in various design flow scenarios and require no or very little hardware overhead. Experiments indicate that significant improvements in compression can be achieved
  • Keywords
    Boolean algebra; automatic test pattern generation; data compression; integrated circuit testing; linear algebra; logic circuits; Boolean matrix; linear algebra; linear decompressor; linear feedback shift register reseeding; linear test data; linear transformation; on chip decompression; scan inversion; symbolic Gaussian elimination; test data compression; Circuit testing; Design methodology; Hardware; Integrated circuit testing; Linear algebra; Linear feedback shift registers; Network-on-a-chip; System testing; Test data compression; Vectors; xor network; Linear decompression; linear feedback shift register (LFSR) reseeding; on-chip decompression; test data compression;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2006.886417
  • Filename
    4019454