DocumentCode :
842409
Title :
Latch-Up Control in CMOS Integrated Circuits
Author :
Ochoa, A. ; Dawes, W. ; Estreich, D.
Author_Institution :
Sandia Laboratories Albuquerque, New Mexico
Volume :
26
Issue :
6
fYear :
1979
Firstpage :
5065
Lastpage :
5068
Abstract :
The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (~9 ¿m p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. This paper will survey latch-up control methods presently employed for weapons and space applications on present (~9 ¿m p-well) CMOS and will indicate the extent of their applicability to VLSI designs.
Keywords :
CMOS integrated circuits; CMOS process; Gold; Impedance; Laboratories; Neutrons; Semiconductor device modeling; Thyristors; Very large scale integration; Weapons;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.1979.4330274
Filename :
4330274
Link To Document :
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