Title :
A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities
Author :
Ribner, David B. ; Baertsch, Richard D. ; Garverick, Steven L. ; McGrath, Donald T. ; Krisciunas, Joseph E. ; Fujii, Toshiaki
Author_Institution :
General Electric Corp. Res. & Dev., Schenectady, NY, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2-μm CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio of 93 and 90 dB at a signal-to-distortion ratio of 93 dB for sample rates of 24 and 80 kHz, respectively
Keywords :
CMOS integrated circuits; analogue-digital conversion; modulators; 1.2 micron; 24 to 80 kHz; 90 to 93 dB; ADC; CMOS; double-poly technology; first-stage integrator; multistage; ratioless input circuitry; sigma-delta modulator; third-order; unconditionally stable; CMOS technology; Circuit testing; Degradation; Delta-sigma modulation; Multi-stage noise shaping; Noise shaping; Operational amplifiers; Quantization; Signal resolution; Signal to noise ratio;
Journal_Title :
Solid-State Circuits, IEEE Journal of
