A high-speed current-multiplexed sample-and-hold amplifier with low hold step

A monolithic high-speed sample-and-hold amplifier is described. It minimizes the hold step via a new circuit architecture. This design takes advantage of the speed of open-loop sample-and-hold circuits during the sample mode and cancellation of charge injection by duplicating and feeding it through a second amplifier during the hold mode. The unique feature of the design is an acquisition time of 150 ns to 0.01% of a 10-V step including the time required for all internal nodes to settle after the hold command is given. Aperture uncertainty is less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip hold and dummy capacitors and the die size is 8.548 mm² on a junction-field-effect-transistor (JFET) plus complementary bipolar process