Title :
Logic testability of defective floating gate CMOS latches
Author :
Champac, V.H. ; Figueras, Jaume ; Rubio, Albert
Author_Institution :
Dept. d´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The behaviour of a defective CMOS latch cell with floating gate defects is analysed in order to investigate the detection of these defects by logic testing. A large number (40%) of the defects will never be detectable by logic testing. Some of the remaining floating gate defects are also undetectable by logic testing, depending on their defect topologies. The need for other test methods such as IDDQ or delay testing is discussed.
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; logic testing; current testing; defect detection; defect topologies; defective CMOS latch cell; delay testing; floating gate CMOS latches; floating gate defects; logic testing;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19921483
