A 300-MPOS video signal processor with a parallel architecture

Author

Minami, Toshihiro ; Kasai, Ryota ; Yamauchi, Hironori ; Tashiro, Yutaka ; Takahashi, Jun-ichi ; Date, Shigeru

Author_Institution

NTT LSI Lab., of Kanagawa, Japan

Volume

26

Issue

12

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1868

Lastpage

1875

Abstract

A 300-MOPS image digital signal processor (IDSP) including four pipelined date processing units and three parallel input-output (I/O) ports has been developed using a 0.8-μm BiCMOS technology. The IDSP integrates 910000 transistors in a 15.2-mm×15.2-mm area using a macrocell-oriented building-block design environment. The power dissipation was reduced to 1.0 W per 25-MHz instruction cycle, and a TTL-compatible I/O interface was retained by implementing two power supplies-one providing 3 V and the other 5 V. With this performance, a single-board 64/128-kb/s video codec was implemented with four IDSPs

Keywords

BIMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; parallel architectures; pipeline processing; video signals; 0.8 micron; 1 W; 128 kbit/s; 25 MHz; 3 V; 5 V; 64 kbit/s; BiCMOS technology; TTL-compatible I/O interface; image DSP; image digital signal processor; macrocell-oriented building-block design; parallel architecture; pipelined date processing units; power dissipation; video codec; video signal processor; BiCMOS integrated circuits; Data processing; Digital signal processors; ISO standards; Parallel architectures; Signal processing; Signal processing algorithms; Throughput; Video codecs; Video compression;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.104178

Filename

104178