A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI

Author

Okamoto, Fuyuki ; Hagihara, Yasuhiko ; Ohkubo, Chie ; Nishi, Naoki ; Yamada, Hachiro ; Enomoto, Tadayoshi

Author_Institution

NEC Corp., Sagamihara-shi, Kanagawa, Japan

Volume

26

Issue

12

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1885

Lastpage

1893

Abstract

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply

Keywords

BIMOS integrated circuits; VLSI; microprocessor chips; pipeline processing; 0.8 micron; 100 MHz; 13.2 W; 17.3 mm; 200 MFLOPS; 40 kbit; 5 V; 64 bit; BiCMOS; ULSI; clock frequency; five-stage pipelined adder/shifter; five-stage pipelined multiplier/divider/logic operation unit; high-speed circuit techniques; high-speed scientific computation; register file; single-chip; triple-layer metallization; vector operations; vector-pipelined processor; BiCMOS integrated circuits; Clocks; Delay; Frequency; Laboratories; Liquid cooling; Partial differential equations; Registers; Ultra large scale integration; Vector processors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.104180

Filename

104180