Title :
An analog neural network processor with programmable topology
Author :
Boser, Bernhard E. ; Sackinger, Eduard ; Bromley, Jane ; Le Cun, Yann ; Jackel, Lawrence D.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130000 connections and was evaluated in 1 ms
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; neural nets; optical character recognition; special purpose computers; 1 ms; 6 bit; CMOS; OCR; analog neural network processor; analog processing internally; classification networks; convolutional topologies; digital input/output; higher density; neural network; optical character recognition; programmable topology; reduced power dissipation; special-purpose neural network processor; Character recognition; Network topology; Neural networks; Neurofeedback; Neurons; Optical character recognition software; Optical computing; Optical feedback; Optical fiber networks; Power dissipation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
