Speed Error Mitigation for a DSP-Based Resolver-to-Digital Converter Using Autotuning Filters

Modern resolver-to-digital converters (RDCs) are typically implemented using DSP techniques to reduce hardware footprint and enhance system accuracy. However, in such implementations, both resolver sensor and ADC channel unbalances introduce significant errors, particularly in the speed output of the tracking loop. The frequency spectrum of the output error is variable depending on the resolver mechanical velocity. This paper presents the design of an autotuning output filter based on the interpolation of precomputed filters for a DSP-based RDC with a type-II tracking loop. A fourth-order peak and a second-order high-pass filter are designed and tested for an experimental RDC. The experimental results demonstrate significant reduction of the peak-to-peak error in the estimated speed.