A self-learning digital neural network using wafer-scale LSI

Author

Yasunaga, Moritoshi ; Masuda, Noboru ; Yagyu, Masayoshi ; Asai, Mitsuo ; Shibata, Katsunari ; Ooyama, Mitsuo ; Yamada, Minoru ; Sakaguchi, Takahiro ; Hashimoto, Masashi

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

28

Issue

2

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

106

Lastpage

114

Abstract

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 μm CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware

Keywords

CMOS integrated circuits; VLSI; backpropagation; learning systems; neural chips; 0.8 micron; CMOS technology; Si wafers; WSI; back-propagation; defect-handling techniques; digital neural network; dual-network architecture; high fault tolerance; high-speed learning; self-learning digital neurons; signature verification; stock price prediction; wafer-scale integration; Artificial neural networks; CMOS technology; Digital circuits; Hardware; Integrated circuit technology; Large scale integration; Neural networks; Neurons; Silicon; Wafer scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.192041

Filename

192041