Title :
Layout reconstruction of complex silicon chips
Author :
Blythe, Simon ; Fraboni, Beatrice ; Lall, Sanjay ; Ahmed, Haroon ; De Riu, Ugo
Author_Institution :
Cavendish Lab., Cambridge Univ., UK
fDate :
2/1/1993 12:00:00 AM
Abstract :
A semiautomated, fast-turnaround and high-reliability procedure for the layout reconstruction of complex VLSI circuits is presented together with details of the equipment and processes employed. The techniques have been verified using both simple CMOS gate array chips and complex VLSI microprocessor circuits and may be applied, in principle, to arbitrarily large or complex devices
Keywords :
EBIC; VLSI; circuit layout; elemental semiconductors; integrated circuit technology; silicon; CMOS; EBIC analysis; SI; complex VLSI circuits; gate array chips; high-reliability procedure; image processing; layout reconstruction; microprocessor circuits; reverse engineering; Circuits; Data acquisition; Error analysis; Image reconstruction; Libraries; Optical microscopy; Reverse engineering; Scanning electron microscopy; Silicon; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
