Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits

Author

Khare, Jitendra ; Feltham, Derek B I ; Maly, Wojciech

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

28

Issue

2

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

146

Lastpage

156

Abstract

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell´s critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method

Keywords

VLSI; circuit layout; estimation theory; statistical analysis; defect-related yield loss; layout sensitivity; manufacturing defects; reconfigurable VLSI circuits; replicated cells; yield estimation method; Fabrication; Helium; Integrated circuit yield; Logic circuits; Manufacturing; Microprocessors; Random access memory; Substrates; Very large scale integration; Yield estimation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.192046

Filename

192046