Title :
High-performance 0.5 mu m n-MOS technology with thin nitrided oxide as gate dielectric
Author :
da Costa, J.C. ; Guegan, Guillaume ; Lerme, M. ; Rey, A. ; Guerin, M. ; Dal´Zotto, B.
Author_Institution :
Dept. Microelectron., CENG, Grenoble, France
Abstract :
0.5 mu m n-MOS devices and circuits have been fabricated successfully using a thin plasma-nitrided silicon dioxide 13 nm thick, with a nitrogen content at the surface. Individual devices show very good and reproducible behaviour. 101-stage ring oscillators with 46 ps gate delay per stage have been obtained, showing that these new dielectrics will be perfectly compatible with future submicronic technologies.
Keywords :
MOS integrated circuits; metal-insulator-semiconductor devices; semiconductor technology; 0.5 micron; 46 ps; SiO 2; gate dielectric; n-MOS technology; plasma-nitrided silicon dioxide; reproducible behaviour; ring oscillators; submicronic technologies; thin nitrided oxide;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890792
