DocumentCode :
843470
Title :
A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity
Author :
Chicca, Elisabetta ; Whatley, Adrian M. ; Lichtsteiner, Patrick ; Dante, Vittorio ; Delbruck, Tobias ; Del Giudice, Paolo ; Douglas, Rodney J. ; Indiveri, Giacomo
Author_Institution :
Inst. of Neuroinformatics, Univ. of Zurich
Volume :
54
Issue :
5
fYear :
2007
fDate :
5/1/2007 12:00:00 AM
Firstpage :
981
Lastpage :
993
Abstract :
The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons
Keywords :
multichip modules; neural nets; peripheral interfaces; tuning; PCI-AER board; address-event representation; cortical neurons; integrate-and-fire neurons; multichip pulse neuromorphic infrastructure; multiple chips; neural networks; orientation selectivity; peripheral component interconnect board; pulse-mode processing; tuning properties; Asynchronous communication; Biological information theory; Integrated circuit interconnections; Neural network hardware; Neural networks; Neuromorphics; Neurons; Protocols; Pulse modulation; Very large scale integration; Address event representation (AER); VLSI; asynchronous; cooperative–competitive; neural chips; neural networks; neuromorphic; orientation tuning; peripheral component interconnect (PCI)-AER; winner take all (WTA);
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2007.893509
Filename :
4195627
Link To Document :
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