Title :
Improved low-complexity low-density parity-check decoding
Author :
Cui, Z. ; Wang, Z.
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR
fDate :
9/1/2008 12:00:00 AM
Abstract :
A practical low-complexity decoding of low-density parity-check codes is studied. A fast decoding scheme for weighted bit-flipping (WBF) based algorithms is first proposed. Then, an optimised 2 bit decoding scheme and its VLSI architecture are presented. It is shown that the new approach has significantly better decoding performance while having comparable hardware complexity compared with WBF-based algorithms.
Keywords :
VLSI; computational complexity; decoding; parity check codes; telecommunication computing; VLSI; WBF; low-complexity decoding; low-density parity-check decoding; weighted bit-flipping;
Journal_Title :
Communications, IET
DOI :
10.1049/iet-com:20070570
