A nonsorting VLSI structure for implementing the (M, L ) algorithm

Author

Simmons, Stanley J.

Author_Institution

Dept. of Electr. Eng., Queen´´s Univ., Kingston, Ont., Canada

Volume

6

Issue

3

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

538

Lastpage

546

Abstract

A nonsorting structure for implementing the (M, L) algorithm is presented. The processing is based on a survivor selection operation that incorporates parallelism and has an execution time proportional to the product of the logarithm of bM (the number of contender paths), and k (the number of bits used for path metrics). Aside from the path extender(s), the processor area is only a small fraction of the total chip area; most is simply for required storage of path histories and metrics. This means that the structure can support a large M on a single chip. In addition, the structure can be extended to larger M by stacking rows of a few different types of custom chips

Keywords

VLSI; decoding; encoding; Viterbi algorithm; algorithm; channel decoding; contender paths; custom chips; nonsorting VLSI structure; parallelism; path extenders; path histories; path metrics; single chip; source coding; survivor selection operation; trellis coding; Decoding; Helium; Image coding; Memory; Parallel processing; Sorting; Source coding; Speech; Very large scale integration; Viterbi algorithm;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.1922

Filename

1922