Title :
Potential vulnerability of dynamic CMOS logic to soft gate oxide breakdown
Author :
Kaczer, B. ; Groeseneken, G.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
The effect of gate oxide breakdown on a circuit designed to emulate a principle of dynamic CMOS logic is studied experimentally. Retention time of a soft node in the circuit is found to strongly decrease after a soft gate oxide breakdown path leading to the node is created in a pass transistor. Based on this observation, it is argued that some soft breakdowns may degrade soft node retention time below the time necessary for successful evaluation of the nodes charge. Consequently, a soft breakdown event in a dynamic CMOS circuit relying on uncorrected soft nodes may result in the failure of the circuit.
Keywords :
CMOS logic circuits; integrated circuit reliability; semiconductor device breakdown; circuit failure; circuit reliability; dynamic CMOS logic; evaluation inverter; inverting output buffer; pass transistor; soft gate oxide breakdown; soft node retention time; uncorrected soft nodes; CMOS logic circuits; CMOS process; Clocks; Digital circuits; Electric breakdown; Inverters; Lead compounds; Logic design; Logic gates; Stress;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.819912
