Description of limit cycles in sigma-delta modulators

A mathematical framework, based on state-space modeling, for the description of limit cycles (LCs) of 1-bit sigma-delta modulators (SDMs) is presented. It is proved that periodicity in bit output pattern of the SDM implies a periodic orbit in state-space variables. While the state-space description is generally applicable for periodic inputs, the focus is on dc inputs, since this represents the most relevant practical condition. An outcome of the analysis is that, in general, for an Nth-order SDM, at least N-1 initial conditions need to be fixed in order to have LC behavior. Expressions for the minimum disturbance of the input or initial conditions that is needed to break up a LC are also presented. Special focus is given to the case where the disturbance takes the form of "dithering the quantizer", and it is shown that this form of dither is a suboptimal approach to remove LCs. The stability of LCs is determined, and it is demonstrated that a resonator section, as often employed to increase the dynamic range of an SDM, has an adverse effect on LC behavior in that it stabilizes LCs. Furthermore, the experimental observation that high order SDMs are less susceptible to LCs is underpinned. Finally, some examples are provided which illustrate the theoretical results.