Title :
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect
Author :
Azadpour, M.A. ; Kalkur, T.S.
Author_Institution :
Vitesse Semicond. Corp., Colorado Springs, CO, USA
Abstract :
Due to decreasing device sizes and increasing clock speed, interconnect inductance is becoming an important factor in the on-chip delay analysis of deep submicrometer technologies. This delay has been represented as an RC model in the available electric design automation tools. In this paper, we model the on-chip interconnect as a RLC for systems running at multigigahertz frequencies. A static-extraction analysis method optimized for ASICs is detailed. It considers all the lines within the vicinity of the target signal line as return paths.
Keywords :
RLC circuits; circuit optimisation; clocks; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; RC model; RLC; clock interconnect extractor; clock interconnect optimization; design optimization; electric design automation; inductance effect; interconnect inductance; on-chip delay analysis; on-chip interconnect; static-extraction analysis; Batteries; Clocks; Delay; Design automation; Frequency; Inductance; Integrated circuit interconnections; Power system interconnection; System-on-a-chip; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2003.817544
