DocumentCode :
846734
Title :
Multithreaded processor architectures
Author :
Byrd, Gregory T. ; Holliday, Mark A.
Author_Institution :
MCNC, Research Triangle Park, NC, USA
Volume :
32
Issue :
8
fYear :
1995
fDate :
8/1/1995 12:00:00 AM
Firstpage :
38
Lastpage :
46
Abstract :
The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed
Keywords :
computer architecture; microprocessor chips; multiprogramming; idle cycles; instruction streams; latency; multiple concurrent execution streams; multithreaded processor architectures; performance; single processor; time-consuming operation; Application software; Computer architecture; Delay; Hardware; High performance computing; Job shop scheduling; Large-scale systems; Registers; Supercomputers; Yarn;
fLanguage :
English
Journal_Title :
Spectrum, IEEE
Publisher :
ieee
ISSN :
0018-9235
Type :
jour
DOI :
10.1109/6.402166
Filename :
402166
Link To Document :
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