Performance trade-offs of globally clocked data-driven arrays

The support of digital signal processing and control algorithms within cellular arrays is well established. The algorithms that tend to be supported are those with a high degree of homogeneity; however, there are many functions that involve feedback loops and conditionality and, topologically, this can lead to irregular layouts which require resynchronisation mechanisms to ensure that data arrive at the correct processors at the correct times. The authors study a novel method for effecting this resynchronisation. The strategy presented has hardware simplicity, speed and throughput rate close to those of globally clocked systolic arrays, while also having the programming simplicity and the tolerance to data-dependent communication of data-driven arrays. The strategy shown possesses the unusual feature that the adoption of slower individual processing elements can lead to overall faster algorithmic throughput rates. It is further demonstrated that this effect using arbitrary algorithms on a linear array of processors and an array with a feedback loop where both the array size and the data-driven processing element size were altered