• DocumentCode
    846897
  • Title

    Comments on "Minimal multiplier realization of 2-D all-pass digital filters" by K. Manivannan and C. Eswaran

  • Author

    Reddy, P. Sreenivasa ; Swamy, M.N.S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
  • Volume
    36
  • Issue
    8
  • fYear
    1989
  • Firstpage
    1147
  • Lastpage
    1148
  • Abstract
    Points out an error in the above paper (see ibid., vol.CAS-35, p.480-482, 1988) and also shows that the realization as such is not valid for filters of order greater than 1. The comments show that the method can be made to work for any order N, provided the delay network is modified by introducing a few more delay elements.<>
  • Keywords
    all-pass filters; two-dimensional digital filters; delay elements; delay network; order; Adders; Delay; Digital filters; Electronic circuits; Flow graphs; IIR filters; Polynomials; Stability; Testing; Transfer functions;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/31.192433
  • Filename
    192433
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=846897