Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic

To make digital circuits with unreliable devices more reliable has been a design challenge, especially for today´s nanometer-scale technologies. In this paper, we discuss gate replication architecture towards increasing the reliability of individual logic gates. While this architecture is similar to, and a special case of, conventional N-modular redundancy scheme, we provide more interpretation and extend it to the situation where N is an even integer by using threshold logic gate instead of majority voter. We also study the reliability models for generic gates with single-electron tunneling (SET) technology. Both analysis and numerical evaluation suggest that while more redundancy leads to higher reliability in general, the improvement rate depends on individual gate failure rates