DocumentCode
848476
Title
Intermetal dielectric-induced N-field device failure in double-level-metal CMOS process
Author
Kuo, H.H. ; Lin, K.M. ; Liu, C.M. ; Tsai, Rick ; Lin, Mou-Shiung ; Yoo, C.S.
Author_Institution
Taiwan Semiconductor Manuf. Co., Hsin-Chu, Taiwan
Volume
13
Issue
8
fYear
1992
Firstpage
405
Lastpage
407
Abstract
In double-level-metal CMOS production processes, the silicate-based spin-on-glass (SOG) planarization scheme, even without a nitride passivation layer, is observed to cause N-field device failure which appears to be due to positive charges trapped in the SOG sandwich layer. Ultraviolet (UV) exposure and backbias are found to be able to eliminate the field and active device leakage. A mechanism is proposed to explain the formation of the positive charges and the UV curing phenomena.<>
Keywords
CMOS integrated circuits; failure analysis; integrated circuit technology; leakage currents; metallisation; radiation effects; N-field device failure; SOG planarization scheme; UV curing phenomena; UV exposure; backbias; double-level-metal CMOS process; intermetal dielectric; leakage elimination; positive charges; CMOS process; Degradation; Dielectric devices; Dielectric measurements; Diodes; Electric breakdown; Passivation; Planarization; Production; Testing;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.192773
Filename
192773
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