Partial-SOI isolation structure for reduced bipolar transistor parasitics

Author

Burghartz, Joachim N. ; Cressler, John D. ; Warnock, James ; McIntosh, R.C. ; Jenkins, K.A. ; Sun, J.Y.-C. ; Comfort, James H. ; Stork, M.C. ; Stanis, C.L. ; Lee, Wai ; Danner, D.D.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

13

Issue

8

fYear

1992

Firstpage

424

Lastpage

426

Abstract

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.<>

Keywords

bipolar integrated circuits; bipolar transistors; capacitance; delays; emitter-coupled logic; integrated circuit technology; semiconductor technology; semiconductor-insulator boundaries; 24 ps; Gummel characteristics; base resistance; bipolar transistor; collector window width; collector-base capacitance; emitter-base self-aligned bipolar device structure; minimum ECL gate delay; nonoptimized lateral device layout; parasitics reduction; partial-SOI isolation structure; simulations; sublithographic emitter width; switch current; Associate members; Bipolar transistors; Delay; Fabrication; Parasitic capacitance; Silicon; Sun; Surfaces; Switches; Technological innovation;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.192779

Filename

192779