DocumentCode
848570
Title
The accumulation-mode field-effect transistor: a new ultralow on-resistance MOSFET
Author
Baliga, B. Jayant ; Syau, Tsengyou ; Venkatraman, Prasad
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Volume
13
Issue
8
fYear
1992
Firstpage
427
Lastpage
429
Abstract
An ultralow specific on-resistance, vertical channel, power MOSFET structure, based on current conduction via an accumulation layer formed on the surface of a trench (UMOS) gate structure, is described. Two-dimensional numerical simulations and experimental results have been obtained, demonstrating that a specific on-resistance approaching 100 mu Omega -cm/sup 2/ can be obtained for a silicon device capable of blocking 25 V.<>
Keywords
accumulation layers; insulated gate field effect transistors; power transistors; 2D numerical simulation; UMOS gate structure; accumulation layer; accumulation-mode field-effect transistor; power MOSFET structure; ultralow specific on-resistance; vertical channel; Doping; FETs; Leakage current; MOSFET circuits; Numerical simulation; P-n junctions; Power MOSFET; Power supplies; Rectifiers; Silicon devices;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.192780
Filename
192780
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