• DocumentCode
    848727
  • Title

    Datapath synthesis using a problem-space genetic algorithm

  • Author

    Dhodhi, Muhammad K. ; Hielscher, Frank H. ; Storer, Robert H. ; Bhasker, Jayaram

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait
  • Volume
    14
  • Issue
    8
  • fYear
    1995
  • fDate
    8/1/1995 12:00:00 AM
  • Firstpage
    934
  • Lastpage
    944
  • Abstract
    This paper presents a new approach to datapath synthesis based on a problem-space genetic algorithm (PSGA). The proposed technique performs concurrent scheduling and allocation of functional units, registers, and multiplexers with the objective of finding both a schedule and an allocation which minimizes the cost function of the hardware resources and the total time of execution. The problem-space genetic algorithm based datapath synthesis system (PSGA-Synth) combines a standard genetic algorithm with a known heuristic to search the large design space in an intelligent manner. PSGA-Synth handles multicycle functional units, structural pipelining, conditional code and loops, and provides a mechanism to specify lower and upper bounds on the number of control steps. The PSGA-Synth was tested on a set of problems selected from the literature, as well as larger problems created by us, with promising results. PSGA-Synth not only finds the best known results for all the test problems examined in a relatively small amount of CPU time, but also has the ability to efficiently handle large problems
  • Keywords
    VLSI; genetic algorithms; high level synthesis; logic partitioning; pipeline processing; scheduling; PSGA-Synth; concurrent scheduling; cost function; datapath synthesis; design space; functional units; hardware resources; high level synthesis; known heuristic; multicycle functional units; problem-space genetic algorithm; structural pipelining; Algorithm design and analysis; Control system synthesis; Cost function; Genetic algorithms; Hardware; Multiplexing; Pipeline processing; Resource management; Testing; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.402494
  • Filename
    402494