A System Overview of Fastbus

FASTBUS is an emerging standard for a high-speed data acquisition bus designed to meet the requirements of the next generation of large-scale physics experiments. It incorporates several powerful features: a 32-bit address field; high speed (< 100 nsec) 32-bit data transfers; multiple bus segments permitting a high degree of independent and parallel activity; permits multiple controllers on a single segment; a protocol (uniform system-wide) with asynchronous handshaked operations to reliably accommodate different speed devices, but which also allows synchronous nonhandshaked operations for transferring blocks at maximum speed; the ability to broadcast commands from any point in the system to the whole system or to selected portions of it; and the ability to rapidly extract data from large, sparsely populated arrays. The paper describes these features in more detail and briefly reviews the present state of development of the standard.