Characterization of charge trapping in submicrometer NMOSFET´s by gate capacitance measurements

Author

Ling, C.H. ; Yeow, Y.T. ; Ah, L.K.

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore

Volume

13

Issue

11

fYear

1992

Firstpage

587

Lastpage

589

Abstract

Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence.<>

Keywords

capacitance; electron traps; hole traps; insulated gate field effect transistors; interface electron states; acceptor-like interface states; channel shortening; charge trapping; electron trapping; gate capacitance measurements; gate-to-drain capacitance; high gate stress voltage; hole trapping; logarithmic time dependence; low gate stress voltage; net negative charge; net positive charge; stressed junction; submicrometer NMOSFET; Capacitance measurement; Charge measurement; Current measurement; Degradation; Electron traps; Implants; Interface states; MOSFET circuits; Photonic band gap; Stress;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.192848

Filename

192848