InP Drain Engineering in Asymmetric InGaAs/InP MOSFETs

Author

Jiongjiong Mo ; Lind, Erik ; Wernersson, Lars-Erik

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

Volume

62

Issue

2

fYear

2015

fDate

Feb. 2015

Firstpage

501

Lastpage

506

Abstract

The design of the InP drain layer in asymmetric InGaAs/InP MOSFETs has been studied experimentally. The influence of doping and thickness of the InP drain has been carefully measured and compared with the performance with an InGaAs drain, regarding the output conductance, the voltage gain, and the leakage current. It is shown that the introduction of an undoped InP spacer has a profound effect on the transistor characteristics. Finally, the effect of a gate-connected field plate at the InP drain side has also been studied both in dc and RF data.

Keywords

III-V semiconductors; MOSFET; gallium arsenide; indium compounds; leakage currents; semiconductor device models; InGaAs-InP; InP drain layer; asymmetric InGaAs-InP MOSFET; doping; gate-connected field plate; leakage current; output conductance; undoped InP spacer; voltage gain; Doping; Indium gallium arsenide; Indium phosphide; Leakage currents; Logic gates; MOSFET; Tunneling; III--V MOSFET; III-V MOSFET; band-to-band tunneling; drain engineering; leakage current; leakage current.;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2014.2375913

Filename

6980065