Title :
A vertically integrated GaAs bipolar/FET DRAM cell with internal gain
Author :
Ling, Z. Gary ; Cooper, James A., Jr. ; Melloch, Michael R.
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
The authors describe a novel dynamic memory cell incorporating a p-n junction storage capacitor, bipolar write-access transistor (BJT), and a junction field-effect transistor (JFET) for nondestructive readout with internal gain. The bipolar transistor is vertically integrated over the storage capacitor and the JFET is formed from the base region of the BJT. Internal gain improves the signal-to-noise ratio and eliminates the requirement that a specific number of electrons be stored in the cell for reliable readout.<>
Keywords :
DRAM chips; III-V semiconductors; gallium arsenide; monolithic integrated circuits; nondestructive readout; BJT; GaAs; JFET; bipolar write-access transistor; bipolar/FET DRAM cell; dynamic memory cell; internal gain; junction field-effect transistor; nondestructive readout; p-n junction storage capacitor; signal-to-noise ratio; vertically integrated memory cell; Capacitors; Electrons; Etching; FETs; Gallium arsenide; Ohmic contacts; P-n junctions; Random access memory; Read-write memory; Signal to noise ratio;
Journal_Title :
Electron Device Letters, IEEE
