Title :
Comments, with reply, on ´Dual-gate operation and volume inversion in n-channel SOI MOSFETs´ by S. Venkatesan et al
Author_Institution :
Lab. de Physique des Composant a Semicond., CNRS, Grenoble, France
Abstract :
For original paper see ibid., vol.13, no.1, pp.44-6 (Jan. 1992). The commenter disagrees with the suggestion by S. Venkatesan, et al. that dual-channel volume inverted devices do not offer significant current-enhancement advantages, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range. The commenter argues that this suggestion is in contradiction with previous demonstrations and with recent results that experimentally show the advantages of volume inversion. In replying, Venkatesan, et al., maintain that, while volume inversion could cause drain current enhancements in the near threshold region, it does not significantly affect the device characteristics in the strong inversion regime.<>
Keywords :
insulated gate field effect transistors; semiconductor-insulator boundaries; drain current enhancements; dual gate operation; n-channel SOI MOSFET; near threshold region; strong inversion regime; volume inversion; Annealing; Electron devices; Electrostatics; Insulation; MOSFET circuits; Numerical simulation; Silicon on insulator technology; Threshold voltage; Transconductance; Virtual colonoscopy;
Journal_Title :
Electron Device Letters, IEEE