DocumentCode
850
Title
Temperature-Dependent Instability of Bias Stress in InGaZnO Thin-Film Transistors
Author
Geng-Wei Chang ; Ting-Chang Chang ; Jhe-Ciou Jhu ; Tsung-Ming Tsai ; Kuan-Chang Chang ; Yong-En Syu ; Ya-Hsiang Tai ; Fu-Yen Jian ; Ya-Chi Hung
Author_Institution
Dept. of Photonics, Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume
61
Issue
6
fYear
2014
fDate
Jun-14
Firstpage
2119
Lastpage
2124
Abstract
The instability of the gate bias and drain bias stresses is observed at high temperature in amorphous InGaZnO thin-film transistors (a-IGZO TFTs). The transfer characteristics of a-IGZO TFTs at different temperatures are also investigated in this paper. The transfer curve exhibits an apparent subthreshold current stretchout phenomenon at high temperature. The stretchout phenomenon becomes more serious with the increase of the temperature. In addition, thermally induced holes are accumulated by the negative gate voltage and get trapped in the gate dielectric or at the dielectric/channel interface at high temperature. The negative threshold voltage shifts with stress time and this is because the trapped holes induce more electrons. For drain bias stress at high temperature, the transfer curve exhibits an apparent shift during drain bias stress at high temperature compared with the same at room temperature. At high temperature, thermally induced holes are trapped in the gate insulator, especially near the drain region. Capacitance-voltage measurements have been used to prove the nonuniform hole-trapping phenomenon. Furthermore, the simulation of the capacitance-voltage and current-voltage curves also have been applied to confirm the hole-trapping distribution. The obtained results clarify that the instability is caused by nonuniform hole-trapping phenomenon.
Keywords
amorphous semiconductors; capacitance measurement; curve fitting; stability; temperature; thin film transistors; transfer functions; voltage measurement; InGaZnO; a-IGZO TFT; amorphous thin-film transistors; capacitance-voltage curves; capacitance-voltage measurements; channel interface; current-voltage curves; dielectric interface; drain bias stresses; gate bias stresses; gate dielectric; gate insulator; hole-trapping distribution; negative gate voltage; negative threshold voltage; nonuniform hole-trapping phenomenon; subthreshold current stretchout phenomenon; temperature-dependent instability; thermally induced holes; transfer characteristics; transfer curve; Educational institutions; Logic gates; Stress; Temperature; Temperature measurement; Thin film transistors; Bias stress; indium gallium zinc oxide (IGZO); technology computer-aided design (TCAD); temperature; thin-film transistors (TFTs); thin-film transistors (TFTs).;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2014.2319105
Filename
6813654
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