Title :
New architecture for parallel multipliers
Author :
Wang, Zhongde ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
fDate :
6/18/1992 12:00:00 AM
Abstract :
An architecture for parallel multipliers, based on 2 bit full adders, is proposed. Multipliers built in this way possess the same structure as previously published five-counter multipliers, but with fewer cells and a reduction of one stage. The architecture is particularly suited to nFET complex block pipelined dynamic logic, and the 2 bit adder cell appears to be more efficient than the five-counter cell.
Keywords :
MOS integrated circuits; digital arithmetic; integrated logic circuits; multiplying circuits; 2 bit adder cell; 2 bit full adders; complex block pipelined dynamic logic; domino logic; fewer cells; parallel multipliers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19920809
