DocumentCode :
850695
Title :
Hardware-software partitioning and pipelined scheduling of transformative applications
Author :
Chatha, Karam S. ; Vemuri, Ranga
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Volume :
10
Issue :
3
fYear :
2002
fDate :
6/1/2002 12:00:00 AM
Firstpage :
193
Lastpage :
208
Abstract :
Transformative applications are computation intensive applications characterized by iterative dataflow behavior. Typical examples are image processing applications like JPEG, MPEG, etc. The performance of embedded hardware-software systems that implement transformative applications can be maximized by obtaining a pipelined design. We present a tool for hardware-software partitioning and pipelined scheduling of transformative applications. The tool uses iterative partitioning and pipelined scheduling to obtain optimal partitions that satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function that minimizes the initiation interval of the final design. We present techniques for generation of good initial solution and search-space limitation for the branch and bound algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a novel retiming heuristic that optimizes the initiation interval, number of pipeline stages, and memory requirements of the particular design alternative. We evaluate the performance of the retiming heuristic by comparing it with an existing technique. The effectiveness of the entire tool is demonstrated by a case study of the JPEG image compression algorithm. We also evaluate the run time and design quality of the tool by experimentation with synthetic graphs.
Keywords :
VLSI; coprocessors; data compression; data flow computing; data flow graphs; embedded systems; hardware-software codesign; pipeline processing; processor scheduling; shared memory systems; tree searching; video coding; JPEG algorithm; area constraints; branch and bound approach; custom hardware coprocessors; design quality; directed acyclic graph; embedded hardware-software systems; hardware-software partitioning; image processing applications; initiation interval; iterative dataflow behavior; iterative partitioning; local memory; memory requirements; number of pipeline stages; objective function; optimal partitions; pipelined design; pipelined scheduling; retiming heuristic; search-space limitation; shared memory; synthetic graphs; system-level design; task graph; timing constraints; transformative applications; uniprocessing system; Application software; Coprocessors; Decoding; Embedded system; Image coding; Partitioning algorithms; Pipeline processing; Processor scheduling; Signal processing algorithms; Transform coding;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2002.1043323
Filename :
1043323
Link To Document :
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