DocumentCode :
850714
Title :
Analysis and Design of Finite-Length LDPC Codes
Author :
Yue, Guosen ; Lu, Ben ; Wang, Xiaodong
Author_Institution :
NEC Labs. America Inc, Princeton, NJ
Volume :
56
Issue :
3
fYear :
2007
fDate :
5/1/2007 12:00:00 AM
Firstpage :
1321
Lastpage :
1332
Abstract :
We consider the performance analysis and code construction of finite-length low-density parity-check (LDPC) codes. First, by convergence analysis based on the extrinsic information evolution, we analyze the performance of both regular and irregular finite-length LDPC codes under iterative decoding. Next, by focusing on a special class of LDPC codes, namely, systematic irregular repeat-accumulate (IRA) codes, we propose a design procedure to construct finite-length LDPC codes. In addition to giving rise to a simple encoding structure, the special structure of IRA codes can be exploited to introduce unequal protection with cycle control for different types of nodes in the factor-graph code representation. We propose a modified bit-filling algorithm that leads to the construction of a set of finite-length IRA codes with low error floors
Keywords :
iterative decoding; parity check codes; bit filling algorithm; convergence analysis; extrinsic information evolution; factor graph code; finite length LDPC codes; irregular repeat-accumulate codes; iterative decoding; low-density parity-check codes; unequal protection; Code standards; Delay; Design optimization; Information analysis; Iterative decoding; Laboratories; Parity check codes; Performance analysis; Throughput; Turbo codes; Code design; finite length; irregular repeat-accumulate (IRA) codes; low-density parity-check (LDPC) codes; performance analysis;
fLanguage :
English
Journal_Title :
Vehicular Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9545
Type :
jour
DOI :
10.1109/TVT.2007.895603
Filename :
4201074
Link To Document :
بازگشت