Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design

Author

Navarro, S. João ; Van Noije, Wilhelmus A M

Author_Institution

Dept. of Electron. Syst., Sao Paulo Univ., Brazil

Volume

10

Issue

3

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

301

Lastpage

308

Abstract

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.

Keywords

CMOS digital integrated circuits; circuit simulation; high-speed integrated circuits; integrated circuit design; low-power electronics; prescalers; 0.8 micron; 2.19 GHz; 46 mW; 5 V; data handling rates; data path connection; digital high-speed design; double input/output data throughput; dual-modulus prescaler; extended TSPC structures; extended true-single-phase-clock CMOS circuit technique; gigahertz CMOS circuit design; low power; operation rate; power consumption; simulations; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Circuit synthesis; Clocks; Energy consumption; Latches; Read only memory; Throughput;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2002.1043333

Filename

1043333