Title :
Compatible cell connections for multifamily dynamic logic gates
Author :
Ortiz, Rolando Ramírez ; Knight, John P.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fDate :
6/1/2002 12:00:00 AM
Abstract :
Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.
Keywords :
CMOS logic circuits; integrated circuit design; logic design; logic gates; timing; CMOS logic gates; circuit design rules; compatible cell connections; connection rules; dynamic logic gate synthesis; feasible connections; logic circuit cells; multifamily dynamic logic gates; timing framework; true-single-phase-clock; waveform response graphs; CMOS logic circuits; Capacitance; Circuit synthesis; Energy consumption; Latches; Life members; Logic circuits; Logic design; Logic gates;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.1043336
