A bus energy model for deep submicron technology

Author

Sotiriadis, Paul P. ; Chandrakasan, Anantha P.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

Volume

10

Issue

3

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

341

Lastpage

350

Abstract

We present a comprehensive mathematical analysis of the energy dissipation in deep submicron technology buses. The energy estimation is based on an elaborate bus model that includes distributed and lumped parasitic elements that appear as technology scales. The energy drawn from the power supply during the transition of the bus is evaluated in a closed form. The notion of the transition activity of an individual line is generalized to that of the transition activity matrix of the bus. The transition activity matrix is used for statistical estimation of the power dissipation in deep submicron technology buses.

Keywords

CMOS digital integrated circuits; SPICE; VLSI; integrated circuit design; integrated circuit modelling; low-power electronics; system buses; timing; CMOS inverters; HSPICE simulations; VLSI; bus model; bus transition activity matrix; closed form energy evaluation; deep submicron technology buses; digital circuit; distributed parasitic elements; energy dissipation; energy estimation; line transition activity; lumped parasitic elements; mathematical analysis; power reduction; statistical estimation; timing issues; Capacitors; Energy dissipation; Integrated circuit interconnections; Mathematical analysis; Parasitic capacitance; Power dissipation; Power supplies; Repeaters; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2002.1043337

Filename

1043337