DocumentCode :
851497
Title :
A very high speed architecture for simulated annealing
Author :
Abramson, David
Author_Institution :
Commonwealth Sci. & Ind. Res. Organ., Carlton, Vic., Australia
Volume :
25
Issue :
5
fYear :
1992
fDate :
5/1/1992 12:00:00 AM
Firstpage :
27
Lastpage :
36
Abstract :
A class of scheduling problems that can be modeled by using very simple cost measures, namely, counting costs and distance-measure costs, is presented. These measures can be incorporated into a simulated annealing algorithm, providing a robust system for solving such scheduling problems. A special-purpose computer architecture that supports the simulated annealing of such problems is described. This architecture provides speeds greatly surpassing those of conventional workstations and supercomputers using the same algorithm.<>
Keywords :
computer architecture; scheduling; simulated annealing; counting costs; distance-measure costs; robust system; scheduling problems; simple cost measures; simulated annealing algorithm; special-purpose computer architecture; very high speed architecture; Computational modeling; Computer architecture; Computer simulation; Costs; Processor scheduling; Robustness; Scheduling algorithm; Simulated annealing; Supercomputers; Workstations;
fLanguage :
English
Journal_Title :
Computer
Publisher :
ieee
ISSN :
0018-9162
Type :
jour
DOI :
10.1109/2.144393
Filename :
144393
Link To Document :
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